Sub-circuit Cell-based High-frequency Analog Integrated Circuit Design in Scaled CMOS.

Sub-circuit Cell-based High-frequency Analog Integrated Circuit Design in Scaled CMOS.

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To demonstrate the sub-circuit cell-based design methodology, a wideband receiver RF front end including a low-noise amplifier (LNA) and a mixer is designed and fabricated in a 130-nm CMOS process. The design of the LNA achieves a maximum power gain of 16.2 dB, an input return loss of greater than 11.0 dB, and a minimum noise figure of 2.8 dB, while consuming only 6.7 mW from a 1.2-V supply. The mixer achieves a voltage conversion gain of 5.3 to 8.2dB, a single-sideband noise figure of 9.6 to 13.5dB between 3 to 7 GHz with 5.8 mW power consumption from a 1.2-V supply.To demonstrate the sub-circuit cell-based design methodology, a wideband receiver RF front end including a low-noise amplifier (LNA) and a mixer is designed and fabricated in a 130-nm CMOS process.


Title:Sub-circuit Cell-based High-frequency Analog Integrated Circuit Design in Scaled CMOS.
Author: Dong Hun Shin
Publisher: - 2009
ISBN-13:

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